FIG. 1 corresponds to FIG. 1 of U.S. Pat. No. 8,513,761 (incorporated by reference), which illustrates an example of an electric circuit of a pixel of an image sensor of rolling shutter type.
A photodiode D is connected to a sense node S by a transfer transistor T1 having its gates connected to a terminal TG1. A read circuit comprises an N-channel MOS transistor RST, interposed between a power supply rail Vdd and sense node S, and two series-connected N-channel MOS transistors SF and RD. The drain of transistor SF is connected to power supply rail Vdd. The source of transistor RD is connected to a terminal P, itself connected to a processing circuit (not shown). The gate of read transistor SF, assembled as a source follower, is connected to sense node S. Generally, the control signals of transistors T1, RD, and RST are supplied by one or a plurality of control circuits (not shown) of the image sensor and may be supplied to all the pixels of a same row of the pixel array of the sensor.
In a sensor of rolling shutter type, the pixels receive an illumination and store photogenerated charges in photodiode D during an integration phase, transistor T1 then being in the off state. The pixels are read during a read phase. The read phase comprises an operation of transferring the photogenerated charges from photodiode D to sense node S by setting transistor T1 to the on state, and an operation of reading the voltage of sense node S with the read circuit. This voltage is representative of the quantity of charges photogenerated during the integration phase and forms an output signal of the pixel.
Such a sensor is said to be of rolling shutter type since the transfer operation and the read operation are carried out for all the pixels in a row before being successively carried out for the other pixel rows of the array. The rows of the array thus capture a scene but at times shifted with respect to one another.
FIG. 2 schematically illustrates an example of an electric circuit of an image sensor pixel of global shutter type.
As in FIG. 1, the circuit of FIG. 2 comprises photodiode D, sense node S, transistor T1, and the read circuit formed of transistors RST, RD, and SF, the read circuit being connected to sense node S in the same way as in FIG. 1. Unlike the circuit of FIG. 1, transfer transistor T1 is connected to a memory cell 1 rather than to sense node S. Further, a transfer transistor T2 having its gate connected to a terminal TG2 is connected between memory cell 1 and sensor node S.
In a sensor of global shutter type, the read phase comprises a transfer operation during which transistor T1 is turned on, the photogenerated charges stored in photodiode D being then transferred to memory cell 1. The transfer operation is simultaneously carried out for all the pixels in the array, which enables to store a complete image in all memory cells 1 of the sensor. Once the transfer operation has been performed, transistor T1 is set back to the off state and a new integration phase may start while the read phase carries on. The read phase then comprises an additional transfer operation during which transistor T2 is set to the on state to transfer the charges stored in memory cell 1 to sense node S. In the same way as in a sensor of rolling shutter type, the voltage of node S is then read during a read operation. The additional transfer operation and the operation of reading node S are carried out for all the pixels in a row before being successively repeated for the other rows of the array.
Due to the fact that a complete image is stored in all the memory cells 1 of the sensor, this provides images without the defects due to the time shifts which may occur in images obtained from an image sensor of rolling shutter type. However, as compared with a pixel of rolling shutter type, in a pixel of global shutter type, it is necessary to further provide a memory cell and a transistor.
FIG. 3 corresponds to FIG. 5 of U.S. Pat. No. 8,513,761, which is a cross-section view of an example of a pixel of a sensor of rolling shutter type.
The pixel comprises a portion of a lightly-doped N-type silicon substrate 11 (N−) laterally delimited by a conductive wall 24, insulated by an insulator 23, connected to a terminal Vwall. On the front or upper surface side of the pixel and in a substantially central area of the pixel, transfer transistor T1 comprises a vertical ring-shaped electrode 16 insulated by an insulator 15. An interconnection structure, not shown, rests on the front surface of the pixel and connects insulated electrode 16 to terminal TG1. Electrode 16 laterally delimits a region comprising a lower lightly-doped N-type portion 17 (N−), and an upper heavily-doped N-type portion 18 (N+). Upper portion or charge collection area 18 is directly connected to node S by the interconnection structure. Lower portion or transfer area 17 extends from charge collection area 18 down to a depth substantially equal to or smaller than that of electrode 16. A heavily-doped P-type well 13 (P+) penetrates into substrate 11 down to a depth smaller than or substantially equal to that of insulated vertical electrode 16. Well 13 has various transistors formed therein, for example, transistors RD (not shown), RST, and SF of the pixel read circuit. A heavily-doped P-type layer 19 (P+) is arranged at the lower surface of substrate 11. Further, the back side or lower surface of the pixel is covered with a color filter 20 and with a lens 21.
During an integration phase, the pixel receives an illumination on its back side, whereby charges are photogenerated and accumulate in substrate 11. Thus, substrate 11 corresponds to photodiode D of the circuit of FIG. 1 and forms a photosensitive area designated, like the substrate, with reference numeral 11. During the integration phase, transistor T1 is in the off state. This transistor is set to the on state during the transfer operation of the read phase such as described in relation with FIG. 1.
The pixel of FIG. 3 has many advantages. In particular, this pixel may have very small dimensions.
It would be desirable to have a pixel adapted to a control of global shutter type and which keeps the advantages of very small dimensions of the pixel of FIG. 3.
It would also be desirable to have a pixel of global shutter type which comprises correction means to decrease or suppress the influence of parasitic charges on the output signal of the pixel.